1. Technical Field
Embodiments relate to a semiconductor apparatus, and more particularly, to a technique for constituting an internal power supply voltage circuit of the semiconductor apparatus having a configuration that a plurality of semiconductor chips are stacked one on top of another.
2. Related Art
A semiconductor apparatus typically receives an external power supply voltage to generate an internal voltage having various voltage levels, and operates an internal circuit of the semiconductor apparatus by using the internal voltage.
FIG. 1 is a block diagram showing a configuration of a power supply voltage generating unit of a typical semiconductor apparatus.
Referring to FIG. 1, the power supply voltage generating unit includes a reference voltage generating unit 1000 and an internal voltage generating unit 2000. The reference voltage generating unit 1000 generates a reference voltage VREF which has a constant level regardless of variations of a power supply voltage VDD applied from outside (i.e., from a pad). The internal voltage generating unit 2000 generates an internal voltage VINT by using the reference voltage VREF. The internal voltage generating unit 2000 is configured to compare the reference voltage VREF with a feedback voltage (not shown) divided from the internal voltage VINT and control the level of the internal voltage VINT based on the comparison result so that the level of the internal voltage VINT can be maintained at a constant level. In other words, the internal voltage generating unit 2000 performs an internal operation so that the level of the internal voltage VINT can reach a target level again if the level of the internal voltage VINT is below or above the target level.
Meanwhile, various package schemes have recently been proposed so as to achieve high integration of a semiconductor apparatus. Specifically, a chip stack scheme that a plurality of semiconductor chips are stacked one on top of another to constitute a single semiconductor apparatus uses a through-chip via so as to commonly transfer a signal to the plurality of semiconductor chips. In general, the through-chip via is referred to as a though-silicon via (TSV) because the semiconductor chip is generally manufactured with a silicon wafer.
In addition, the plurality of stacked semiconductor chips can be classified into a master chip and one or more slave chips. The master chip is configured to perform an operation for communicating a signal with outside and controlling the slave chip. And, the one or more slave chips are each configured to perform a specific operation under the control of the master chip. For example, in case of the semiconductor memory apparatus, the master chip may include a peripheral circuit related to a control signal and an input/output operation of a signal whereas the slave chip may include a memory bank configured to store data. For reference, such a circuit configuration assigned to the master chip and the slave chip can be varied depending on specific needs.
FIG. 2 is a diagram showing a configuration of a typical stacked semiconductor apparatus.
Referring to FIG. 2, the typical stacked semiconductor apparatus includes a master chip MASTER CHIP and a plurality of slave chips SLAVE CHIP1 to SLAVE CHIP4. The master chip MASTER CHIP and the plurality of slave chips SLAVE CHIP1 to SLAVE CHIP4 are staked one on top of another, and a plurality of through-silicon vias (TSVs) 101, 102, 103 and 104 are penetrating and coupling the master chip MASTER CHIP and the plurality of slave chips SLAVE CHIP1 to SLAVE CHIP4 together. For convenience of description, a plurality of sub through-silicon vias (TSVs) vertically penetrating the respective semiconductor chips will be referred to as a single through-silicon via (TSV) hereinafter.
The semiconductor apparatus including the master chip MASTER CHIP and the plurality of slave chips SLAVE CHIP1 to SLAVE CHIP4 has a configuration that a power supply voltage circuit and the peripheral circuit are concentrated in the master chip MASTER CHIP so as to secure a net die.
Therefore, as shown in FIG. 2, the master chip MASTER CHIP includes a reference voltage generating unit 11, a reference voltage trimming unit 12, and an internal voltage generating unit 13, and transfers an internal voltage VINT generated in the internal voltage generating unit 13 to the plurality of slave chips SLAVE CHIP1 to SLAVE CHIP4 through the plurality of TSVs 101, 102, 103 and 104. The plurality of slave chips SLAVE CHIP1 to SLAVE CHIP4 respectively perform an internal operation by using the internal voltage VINT transferred via the plurality of TSVs 101, 102, 103 and 104. In other words, first and second logic units included in the respective slave chips SLAVE CHIP1 to SLAVE CHIP4 perform the internal operation by using the internal voltage VINT generated in the master chip MASTER CHIP as an operation power supply voltage.
The reference voltage trimming unit 12 trims a reference voltage VREF0 generated from the reference voltage generating unit to output a trimmed reference voltage VREF. Operation characteristics of the internal circuit of the semiconductor apparatus can be varied due to a variation of process, voltage and temperature (PVT). Specifically, due to the variation of the process, a level of the reference voltage VREF0 generated from the reference voltage generating unit 11 or a level of the internal voltage VINT may deviate from a target level. Specifically, since the reference voltage VREF0 is a main factor that determines a reference level in the internal power supply voltage circuit, a role of the reference voltage trimming unit 12 configured to trim the reference voltage VREF0 is very important.
Meanwhile, the respective slave chips SLAVE CHIP1 to SLAVE CHIP4 of the semiconductor apparatus of FIG. 2 receive the internal voltage VINT generated from the master chip MASTER CHIP via the plurality of TSVs 101, 102, 103 and 104, and use the internal voltage VINT as the operation power supply voltage of the internal logic unit. At this time, since the plurality of slave chips SLAVE CHIP1 to SLAVE CHIP4 can have different characteristics from each other due to the variation of the process, a level of the internal voltage VINT that enables the respective slave chips SLAVE CHIP1 to SLAVE CHIP4 to operate optimally may also be different from each other. However, since the semiconductor apparatus of FIG. 2 commonly transfers the internal voltage VINT generated from the master chip MASTER CHIP to the plurality of slave chips SLAVE CHIP1 to SLAVE CHIP4, it is difficult to generate an optimal and common internal voltage VINT that can thoroughly compensate the variation of the process of the respective slave chips SLAVE CHIP1 to SLAVE CHIP4.